This invention relates to a semiconductor apparatus and, in particular, to a semiconductor apparatus having a wiring pattern formed in a region under a bonding pad.
Following development of a highly-integrated semiconductor apparatus, a device pattern is more and more miniaturized and a design rule thereof becomes finer year after year. However, in comparison with the progress of miniaturization of the device pattern, the progress in miniaturization of a bonding pad of the semiconductor apparatus is little due to limitation imposed upon a bonding technique and an accuracy of a bonding apparatus. In the semiconductor apparatus, for example, in a dynamic random access memory (DRAM), reduction in chip size has a significant influence upon cost reduction in order that mass production is carried out. In order to reduce the chip size, it is necessary to reduce a bonding pad area and to effectively use a region under the bonding pad area. As one approach for effectively using the bonding pad area, it is considered to form the bonding pad on a device region or a wiring region while the bonding pad is traditionally formed in a region except the device region and the wiring region.
A related bonding pad comprising a two-layer aluminum wiring structure is shown in FIG. 1. In a region under the bonding pad formed by a #2 aluminum pad wiring 20 as an upper wiring layer, a #1 aluminum wiring 10 as a lower wiring layer similar in size to the bonding pad is disposed. At both ends of the bonding pad, #1 aluminum pad connecting wirings 13 as internal wirings and the #2 aluminum pad wiring 20 are connected to each other by #1-#2 layer conductive plugs 40. The #1 aluminum wiring 10 is, throughout a substantially entire area thereof, connected to the #2 aluminum pad wiring 20 via another #1-#2 layer conductive plug 40. The #1-#2 layer conductive plugs 40 serve as piles (or anchor bolts) for preventing the #2 aluminum pad wiring 20 from being peeled off after bonding. With the above-mentioned structure, since the #1 aluminum wiring 10 is present in the region under the bonding pad, the lower wiring layer can not be used as a signal wiring, resulting in an increase in chip size.
In FIG. 1, a polyimide 5 is provided with an opening.
Referring to FIG. 2, description will be made of a case where the #1 aluminum wiring 10 and the #1-#2 layer conductive plug 40 formed throughout the substantially entire area under the bonding pad are not used. In FIG. 2, instead of the #1 aluminum wiring 10 under the bonding pad in FIG. 1, a #1 aluminum pass-through wiring 12 as a signal wiring can be arranged. Thus, in case where the bonding pad of the #2 aluminum pad wiring 20 is not peeled off from an interlayer insulating film by a mechanical shock during bonding, the #1 aluminum pass-through wiring 12 can be disposed under the bonding pad. However, if the pass-through wiring 12 is extended under the bonding pad, the pass-through wiring 12 may be broken due to the mechanical shock during bonding.
Japanese Unexamined Patent Application Publication JP S59-181041 A discloses such a technique of forming the lower wiring layer in the region under the bonding pad. In the above-mentioned publication, however, the wiring under the bonding pad is limited to a wiring having a large wiring width in order to prevent breakage due to the mechanical shock during bonding. In addition, in the structure disclosed in the above-mentioned publication, the bonding pad of the #2 aluminum wiring is easily peeled off after bonding.
In an etching step or a CMP (Chemical Mechanical Polishing) step, an optimum production condition is different depending upon the density of the pattern. In FIG. 1, a pattern as the lower wiring layer similar in size to the bonding pad is disposed in the region under the bonding pad. Therefore, the pattern is dense as compared with an internal circuit portion. In FIG. 2, depending upon the number of wirings extended in the region under the bonding pad, the pattern may be sparse as compared with the internal circuit portion. Therefore, the density of the lower wiring pattern under the bonding pad in FIG. 1 or 2 is considerably different as compared with that of the internal circuit portion. This results in a difficulty in determining etching or CMP conditions during a diffusion process.
Another approach for effectively using the bonding pad area is disclosed in Japanese Unexamined Patent Application Publication JP 2005-166959 A. Specifically, a gate region under the bonding pad is protected by a strengthening via. In Japanese Unexamined Patent Application Publication JP 2005-116788 A, a via is formed in order to relax a stress of an insulating film under the bonding pad. However, these publications do not disclose a technique of arranging a fine wiring in the region under the bonding pad. Further, no disclosure is made of a technique of arranging a striped plug wiring in the region under the bonding pad and providing a conductive plug on the plug wiring in order to achieve a density same as that in the internal circuit portion.
As described above, in the semiconductor apparatus, it is desired to reduce the chip size for the purpose of cost reduction. In order to reduce the chip size, it is effective to utilize the region under the bonding pad. Accordingly, it is desired to develop a technique of arranging a fine wiring in the region under the bonding pad so as to effectively use the region under the bonding pad. However, because the pad wiring is peeled off or the pass-through wiring is broken due to the mechanical shock during bonding, it is impossible to arrange the fine pass-through wiring in the region under the bonding pad. Therefore, it is impossible to effectively utilize the region under the bonding pad.